CS 202 - Notes 2018-11-19
Making memory circuits
The examples can be found in the latch_flipflop.circ
SR latch
We cross-couple a pair of NOR gates to get this simple latch. Note that in the truth table, we have to take into consideration the values of the outputs when S and R change. There isn't really a separate "old Q" -- it is just an expression of time. We have to consider all of the fluctuations until the circuit stabilizes (if it does).
| S | R | old Q | old Q' | new Q | new Q' | notes |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | toggle | toggle | Bad |
| 0 | 0 | 0 | 1 | 0 | 1 | Hold |
| 0 | 0 | 1 | 0 | 1 | 0 | Hold |
| 0 | 0 | 1 | 1 | toggle | toggle | Bad |
| 0 | 1 | X | X | 0 | 1 | RESET |
| 1 | 0 | X | X | 1 | 0 | SET |
| 1 | 1 | X | X | 0 | 0 | ILLEGAL |
We declare the input 11 to be illegal because it breaks our labeling of the second output as Q', and it sets us up for our bad state.
Our bad state is particularly bad not because it toggles, but because it won't except in a simulator. Manufacturing tolerances mean that every gate will have a slightly different propagation delay, so we will settle at either 01 or 10, but it will depend on which instance of the circuit we have which one of those happens.
JK latch
The JK Latch addresses the ILLEGAL state by adding a pair of AND gates to the front of the latch that are ANDed to the outputs. Since the SR latch won't put 11 on the output, we will never get a 11 on the input of it either.
However, it will still toggle if we set both j and k to 1. The difference being that it won't settle into an unknown state.
JK flip-flop
An issue with latches is that they are "transparent". Any changes we make to the input are immediately reflected on the output. If you imagine the latch being both the input of a combinational circuit (like an adder) and the destination of the result (this x = x + 1), we may get an answer as intermediate results are still bubbling through the circuit and then changing the input.
We fix this by adding a clock signal. When the clock is low, we can make any changes we like, and the result will not be propagated. We tune the clock to have a frequency such that any operation in our circuits can be accomplished while it is 0.
JK master slave flip-flop
By pairing two JK flip-flops with opposing clock sensitivities, we can eliminate the oscillation on the 11 input. The flip-flop will still toggle back and forth, but it will be in time with the clock.
D flip-flop
The D flip-flop is a slightly different approach that allows it to be edge-triggered, which is to say, the flip-flop stores the value on the input when the clock changes from 0 to 1, but it is blind to any further changes. This makes timing easier since we don't have to worry about the input being stable.