ARM Reference
ADD: Add (immediate)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0|1|0 1 0 0|S| Rn | Rd | imm12 |
+---------------------------------------------------------------+
assembly: add Rd, Rn, #imm12
effect: Rd <- Rn + extend(imm12)
example: e283300a add r3, r3, #10
ADD: Add (register)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0|0|0 1 0 0|S| Rn | Rd | | Rm |
+---------------------------------------------------------------+
assembly: ADD Rd, Rn, Rm
effect: Rd <- Rn + Rm
example: e0823003 ADD r3, r2, r3
AND: Bitwise And (immediate)
Note that & is the symbol for bitwise AND
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0 1 0|0 0 0|S| Rn | Rd | imm12 |
+---------------------------------------------------------------+
assembly: AND Rd, Rn, Rm
effect: Rd <- Rn & extend(imm12)
example: e2078025 AND r8, r7, #37
AND: Bitwise And (register)
Note that & is the symbol for bitwise AND
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0|0|0 0 0 0|S| Rn | Rd | | Rm |
+---------------------------------------------------------------+
assembly: AND Rd, Rn, Rm
effect: Rd <- Rn & Rm
example: e0023003 AND r3, r2, r3
B: Branch
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| cond |1 0 1 0| offset |
+---------------------------------------------------------------+
assembly: B<cond> #48
effect: if cond evaluates to false, PC <- PC + 4 as normal
if cond evaluates to true, PC <- PC + 4 + sign-extend(offset) * 4
examples: 0a000001 BE #1
1afffff9 BNE #-7
cond:
0 0 0 0 equal (BE)
0 0 0 1 not-equal (BNE)
1 0 1 0 greater-than-or-equal (BGE)
1 0 1 1 less-than (BLT)
1 1 0 0 greater-than (BG)
1 1 0 1 less-than-or-equal (BLE)
1 1 1 0 always (B)
CMP: Compare (immediate)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0 1 1 0|1 0|1| Rn | | imm12 |
+---------------------------------------------------------------+
assembly: CMP Rn, #imm12
effect: condition-code register saves result of comparing contents of Rn
and extend(imm12)
example: e354002a CMP r4, #42
CMP: Compare (register)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0 0 1 0|1 0|1| Rn | | Rm |
+---------------------------------------------------------------+
assembly: CMP Rn, Rm
effect: condition-code register saves result of comparing contents of Rn
example: e1590007 CMP r9, r7
EOR: Bitwise Exclusive OR (immediate)
Note that ^ is the symbol for bitwise XOR
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0 1 0|0 0 1|S| Rn | Rd | imm12 |
+---------------------------------------------------------------+
assembly: EOR Rd, Rn, #imm12
effect: Rd <- Rn ^ extend(imm12)
example: e2278025 EOR r8, r7, #37
EOR: Bitwise xor (register)
Note that ^ is the symbol for bitwise XOR
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0|0|0 0 0 1|S| Rn | Rd | | Rm |
+---------------------------------------------------------------+
assembly: EOR Rd, Rn, Rm
effect: Rd <- Rn ^ Rm
example: e0223003 EOR r3, r2, r3
LDR: Load (base or base+immediate)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 1|0|1 1|0 0 1| Rn | Rt | imm12 |
+---------------------------------------------------------------+
assembly: ldr Rt, Rn, #imm12
effect: Rt <- mem[Rn + zero-extend(imm12)]
example: e596500c ldr r5, r6, #12
Note that when the imm12 is left blank, we get the base address mode, for the assembly we just leave off the immediate value
assembly: ldr Rt, Rn
effect: Rt <- mem[Rn]
example: e5965000 ldr r5, r6
LDR: Load (base + register offset or base + scaled offset)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 1|1|1 1|0 0 1| Rn | Rt | imm5 | |0| Rm |
+---------------------------------------------------------------+
assembly: ldr Rt, Rn, Rm, shift
effect: Rt <- mem[Rn + (Rm << imm5)]
example: e7923105 ldr r3, r2, r5, 2
Note that when the imm5 is left blank, we get base + register offset mode, for the assembly we just leave off the shift value
assembly: ldr Rt, Rn, Rm
effect: Rt <- mem[Rn + Rm]
example: e7923005 ldr r3, r2, r5
MOV: Move (immediate)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0|1|1 1 0 1|S| | Rd | imm12 |
+---------------------------------------------------------------+
assembly: MOV Rd, #imm12
effect: Rd <- extend(#imm12)
example: e3a0200a MOV r2, #10
MOV: Move (register)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0|0|1 1 0 1|S| | Rd | | Rm |
+---------------------------------------------------------------+
assembly: MOV Rd, Rm
effect: Rd <- Rm
example: e1a02003 MOV r2, r3
MVN: Bitwise Negate (immediate)
Note that ~ is the symbol for bitwise NOT
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0 1 1 1|1 1|S| | Rd | imm12 |
+---------------------------------------------------------------+
assembly: MVN Rd, #imm12
effect: Rd <- ~(extend(imm12))
example: e3e0300a MVN r3, #10
MVN: Bitwise Negate (register)
Note that ~ is the symbol for bitwise NOT
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0 0 1 1|1 1|S| | Rd | | Rm |
+---------------------------------------------------------------+
assembly: MVN Rd, Rm
effect: Rd <- ~(Rm)
example: e1e00003 MVN r0, r3
ORR: Bitwise Or (immediate)
Note that | is the symbol for bitwise OR
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0 1 1 1|0 0|S| Rn | Rd | imm12 |
+---------------------------------------------------------------+
assembly: ORR Rd, Rn, #imm12
effect: Rd <- Rn | extend(imm12)
example: e3878025 ORR r8, r7, #37
ORR: Bitwise Or (register)
Note that | is the symbol for bitwise OR
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0|0|1 1 0 0|S| Rn | Rd | | Rm |
+---------------------------------------------------------------+
assembly: ORR Rd, Rn, Rm
effect: Rd <- Rn | Rm
example: e1823003 ORR r3, r2, r3
RSB: Reverse subtraction (immediate)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0|1|0 0 1 1|S| Rn | Rd | imm12 |
+---------------------------------------------------------------+
assembly: rsb Rd, Rn, #imm12
effect: Rd <- extend(imm12) - Rn
example: e263300a rsb r3, r3, #10
RSB: Reverse Subtract (register)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0|0|0 0 1 1|S| Rn | Rd | | Rm |
+---------------------------------------------------------------+
assembly: rsb Rd, Rn, Rm
effect: Rd <- Rm - Rn
example: e0633004 rsb r3, r3, r4
STR: Store (base or base+immediate)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 1|0|1 1|0 0 0| Rn | Rt | imm12 |
+---------------------------------------------------------------+
assembly: str Rt, Rn, #imm12
effect: mem[Rn + zero-extend(imm12)] <- Rt
example: e586500c str r5, r6, #12
Note that when the imm12 is left blank, we get the base address mode, for the assembly we just leave off the immediate value
assembly: str Rt, Rn
effect: mem[Rn] <- Rt
example: e5865000 str r5, r6
STR: Store (base + register offset or base + scaled offset)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 1|1|1 1|0 0 0| Rn | Rt | imm5 | |0| Rm |
+---------------------------------------------------------------+
assembly: str Rt, Rn, Rm, shift
effect: mem[Rn + (Rm << imm5)] <- Rt
example: e7823105 str r3, r2, r5, 2
Note that when the imm5 is left blank, we get base + register offset mode, for the assembly we just leave off the shift value
assembly: str Rt, Rn, Rm
effect: mem[Rn + Rm] <- Rt
example: e7823005 str r3, r2, r5
SUB: Subtract (immediate)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0|1|0 0 1 0|S| Rn | Rd | imm12 |
+---------------------------------------------------------------+
assembly: sub Rd, Rn, #imm12
effect: Rd <- Rn - extend(imm12)
example: e243300a sub r3, r3, #10
SUB: Subtract (register)
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------------------------------------------------------+
| |0 0|0|0 0 1 0| | Rn | Rd | | Rm |
+---------------------------------------------------------------+
assembly: SUB Rd, Rn, Rm
effect: Rd <- Rn - Rm
example: e0423003 SUB r3, r2, r3
Last updated 03/27/2023