Lecture 12 - Instruction Set Architecture

Goals

• Learn what an instruction set architecture is
• Learn what an instruction actually is
• Learn what RISC and CISC architectures are and how they differ

The circuit we designed last time is basically how a computer works

they have a bunch of registers, which we call a register file

they have a bunch of circuitry to perform operations, which we call an arithmetic-logic unit (ALU)

the register file is connected to the inputs of the ALU

and the outputs of the ALU are connected back to the register file

thus an instruction is executed by making sure the correct registers are chosen as inputs, the correct operation is chosen in the ALU, and the correct register is chosen to read its output

this is the start of what we call the datapath of the processor

we execute these instructions in sequence and suddenly we’ve got a program!

Instruction set architecture (ISA)

because this is all hardware, we have to make some decisions before these things are actually manufactured

things like…

• how many registers in the register file?
• how many bits will these registers hold?
• what operations will the ALU perform?
• how do we specify which registers to use for operands?
• how do we specify which register gets the result?

and in fact any manufacturer of computer processors has to decide this

a company like Intel may make different choice than a company like ARM

additionally, needs may change over time and one may wish for a new line of processors that has, e.g., more and larger registers

as we’ll see, however, these choices have a direct effect on the way one writes software

all such choices are codified in what’s called the instruction set architecture (ISA)

thus chips produced by Intel have their particular ISA (they actually have a few, the most prevalent of which are IA-32 and IA-64, which we’ll talk about later in more detail) and ARM has a different ISA

once we figure out the answers to the aforementioned questions, we can bundle the control (or select) wires for each of the components into a big wire

thus we have instructions!

The instructions that are "understood" by the computer are really just bit patterns we apply to this bundle of control signals (sort of)

Note that because different manufacturers use different ISAs, instructions for one won't work on the other.

Deconstructing instructions

Let's deconstruct what we need to perform x = y + z

We’d need to specify:

• the register where the two operands (y and z) reside;
• the operation to perform (addition);
• and which register to put the result in.

let’s assume we have sixteen registers at our disposal and that register 4 is set aside for x, register 2 is set aside for y, and register 5 is set aside for z

sixteen registers means we need 4 bits to identify a particular register (because 2^4 = 16)

let’s also assume that the magical code we feed to the ALU to get it to perform addition is 100 (binary)

thus to cause this code to execute, we’d need to supply the following instruction:

100 0100 0010 0101
 ^    ^    ^    ^
 |    |    |    +--- register allocated to z
 |    |    +-------- register allocated to y
 |    +------------- register allocated to x
 +------------------ addition

then we package up these 15 bits and we suddenly have a single instruction that will make our register-file/ALU combo dance

thus a program will be a sequence of similar instructions that collectively implement the logic required

the 15-bit instruction above uses 4 bits each to represent three different registers (two sources and one destination)

the number of bits used to specify a register is a direct consequence of the design of the processor: we need enough bits to specify any register, so the number of registers in the proc affects the number of bits we need in the instruction

recall that "number of registers" is one of the things defined by the ISA

consequently, the length and format of instructions is also defined by the ISA

RISC and CISC

as you might imagine, different people have different ideas about the details of a given ISA, ideas evolve over time, some are designed for specific purposes, etc

which results in different ISAs existing

not just that, but there are two primary "families" of ISAs and you need to know them

they are RISC (reduced instruction set computers) and CISC (complex instruction set computers)

the instruction set originated by Intel for its processors and since duplicated by other companies to produce compatible processors is (often) called "x86", and is a representative of the CISC family

the ARM company’s ISA (which is itself called "ARM", and is used in the majority of smartphones these days) is a representative of the RISC family

registers

on the topic of registers, one (general) hallmark of RISC ISAs is that they have many general-purpose registers

by "general-purpose" I mean that they don’t have prescribed uses: they can be used as source and destination for nearly any instruction

by contrast, CISC ISAs often have many special-purpose registers meaning that they can only be used for particular purposes

as an example, in x86, the destination register is often always the same: a register called rax

this is a special-purpose register that holds the result of computations (indeed, many x86 instructions do not allow the programmer to specify the destination: it is implicitly hard-wired to be the rax register)

instructions

another difference is in the form of the instructions themselves

CISC architectures have variable-length instructions, meaning that you could see a 16-bit instruction followed by a 32-bit instruction, followed by a 48-bit instruction, all in the same program (even though they’re variable length, they are still a multiple of 8 bits, because these machines all use byte-addressable memory)

When RISC was developed they realized that no one was writing in assembly any more, so why not make things easier for compiler writers. Instructions for a given RISC architecture are all the same length: for example, in the 32-bit version of ARM (which we will shortly become familiar with) all instructions are 32 bits long. There are fewer instructions, so we need to issue more to accomplish the same thing

These are fairly broad characterizations, and the lines are becoming a little blurry

The truth is that even the names were something of a sales pitch by the RISC camp (no one would have chosen "complex" from a marketing perspective)

In the intervening decades the lines between the camps have become fuzzier. RISC architectures are getting more complex, and CISC architectures are adding more registers.

Fetch-execute cycle

A key architectural design choice was made many years ago, with the development of stored program computer The big idea here is that instructions look like data, so why not store them in the same place

So, we add to our picture of our process a couple of components

• memory - a large, addressable place to store all of the instructions and data for the currently running programs
• program counter (PC) - a special register that hold the address of the next instruction to be executed
• instruction register (IR) - a register that holds the instruction currently being executed

different ISA may call these vaguely different things

Running a program is then a process we call the fetch-execute-cycle

• the address stored in the PC is used to read out the next instruction into the IR
• the data in the IR is used to perform the next operation (this can be as simple as a splitter to drive the select lines of the datapath elements)
• while the instruction is being performed, the address stored in the PC is incremented
• repeat

There are some variations in this cycle

Most architectures will take multiple clock cycles for this process since it takes time for data to be read and written to memory

Also, if we want non-linear programs (loops, conditionals, functions) then we need a way to provide an alternative input to the PC than the incrementor

But, this is a reasonable rough approximation of the process

Mechanical level

vocabulary

Skills