## CS 202 - Homework 10

#### Due: Monday, 5/14, at midnight.

This homework completes the Σniac circuit project. You should continue working in the same groups as for HW 9. Submit your homework by midnight on Monday, May 14. If you have a 24h extension left, you have until midnight on Tuesday, but no later please, even if you have more than one extension left.

### Σniac II circuit - control signals

This is the second half of the Σniac circuit project. As discussed in classs, you'll need to add the control circuitry to your Σniac circuit. Here is the timing diagram:

Proceed as follows:

1. Implement a synchronous 2-bit counter from 2 J-K flipflops, followed by a 2-to-4 decoder to generate the timing signals t0, t1, t2, t3.

2. You'll also need 2 J-K flipflops for the signals "E" and "run". The inputs of the "E" FF are "set E" and "reset E"; the outputs are "E" (not-inverted) and "I" (inverted). The "run" should be set (asynchronously) upon a "reset" signal, and reset upon a "halt" signal during t2. (All other flipflops should be reset asynchronously upon a "reset" signal.) Use the output of the "run" FF in an AND gate together with the input clock signal (a "step" button OR a clock) to generate the global clock signal "c". This way, the circuit will start running upon a reset, and stop when a halt signal is reached.

3. Using the above timing diagram, derive equations for all control signals. The inputs to your equations should be the timing signals t0, t1, t2, t3, I, and E, the three opcode bits OP2, OP1, OP0 and/or their decoded signals (ld, sub, add, st, b, bneg, halt), and A7 (the highest bit of the accumulator). The outputs should be all signals that appear in the table. For example, the ld_OP signal can be written as (I AND t1). Similarly, the sub_B signal can be written as (sub AND E AND t2). Feel free to introduce "temporary variables", e.g., a signal E2 = (E AND t2), and a signal stop = (halt AND t2).

Once you have all your equations, implement them using simple AND, OR, and NOT gates and add them to the circuit. Be careful: in the circuit, the signal names are slightly different.

4. The Σniac III - build the next generation Σniac!
Implement a new instruction for the unused opcode 6 (110). At the very least, implement a "clear A" instruction. EXTRA CREDIT will be awarded for more complicated instructions. For example, you could add a "mult" instruction (using Logisim's multiplier), or a "neg" instruction. Or implement a "load immediate" instruction that loads a 5-bit number sign-extended into A. Or maybe an "add immediate" instruction would be more useful. Perhaps best: an "add immediate" instruction that is interpreted as "clear A" if the addend is 0.

Other extra-credit opportunities (harder...):

• Speed up the circuit by using minimum-length cycle sequences.
• See if you can get rid of the B register (also could yield speed-up).
• Make the Σniac a 10-bit or 12-bit machine with 4-bit opcodes.
• Whatever else you can come up with...
Please hand in a written description of the extension you implemented.

#### What to hand in

1. Your Σniac circuit, "zniac.circ". Make sure all subcircuits are labeled and your name(s) are shown on the top-level circuit. Also make sure all registers, flip flops, and memory contents are visible at once and fit on one screen (don't hide them in subcircuits, except perhaps the flip flops; if you do, make sure there are probes showing their state in the top-level circuit). As always, make sure all sub-circuits are properly labeled. If you want, you can hide all the control circuitry in a subcircuit.