Intel 8th Gen Core Die

CS 202 - Spring 2018

Computer Architecture

Announcements

Final Exam: Self-scheduled (pick up at my office), Wed 5/16 - Tue 5/22, 5pm.
The exam is 3 hours (plus an extra 60 minutes if you need them), open book / notes.
You may not use a computer or access material online during the exam.
Study guide

Office hours during finals (5/16-22):
Wed/Thu 1-3pm, Fri 10:30-noon, Mon 5/21 10-noon

Homework

  1. Homework 1, due Monday 2/19. Solutions.
  2. Homework 2, due Monday 2/26. Solutions.
  3. Homework 3, due Monday 3/5. Solutions. Runlong Contest Results.
  4. Homework 4, due Monday 3/12. Solutions.
  5. Homework 5, due Friday 3/23. Solutions.
  6. Homework 6, due Monday 4/9. Solutions.
  7. Homework 7, due Friday 4/20. Scores.
  8. Homework 8, Monday 4/30. Solutions. Scores for 2a.
  9. Homework 9, due Monday 5/7. Solutions.
  10. Homework 10, due Monday 5/14 at midnight.

Lectures

     
DayTopicsReading
1.   M 2/12      Course info, overview, levels of computer languages, sum.c      *T 1, BO 1
2.   W 2/14Number systems, binary, hex, converting between bases         T A, Martin 2.1, Wikipedia:Gibibyte
3.   F  2/16Fixed precision numbers, overflow, C, examples     T A, Martin 2.2-4, [BO 2.1-3]
4.   M 2/19Boolean operations, C, baseB2dec.c Martin 2.5, T 2-2.3.6, *KR 1
5.   W 2/21C: arrays, strings, pointers, computer organization T 2, BO 1
6.   M 2/26Computer organization, fetch-decode-execute, instruction encoding, Σniac         *T 2, T 5.3, BO 1, Σniac handout
7.   W 2/28Σniac programming, abs.zn, abs.hex Σniac handout
8.   F  3/2 HW 3, zniac.c, intro to x86, asmprog.s, main.c BO 3-3.5, T 2.1.3, 5.3-4, x86 registers
9.   M 3/5Arithmetic and logical ops, parameters, shift, lea, HW 4      BO 3-3.5, *silk dress, *HW 4.1a-c
10. W 3/7Push, pop, comparing, branching, sum1to5.s, gdb BO 3.4.4, 3.6
11. F  3/9Branching cont'd, gdb, arrays, arrmax.s BO 3.6, 3.8, HW 4 notes, x86 summary
12. M 3/12Digital circuits, Logisim T 3.1, BO 4.2.1-2
13. W 3/14Multiplexers, decoders, adder/subtractor *T 3.2, HW 5
14. F  3/16 Circuit aesthetics, Logisim bundles, splitters, and subcircuits Logisim documentation
15. M 3/19 Sequential circuits: SR latch, D latch, SR flipflop, D flipflop T 3.3
16. W 3/21Exam Q&A, T flipflop, asynchronous counter
17. F  3/23JK flipflop, synchronous counter, register T 3.3
18. M 4/2Multiplier, shift register HW 6, T 3.3
19. W 4/4 Function calls, hello.s, hello2.s *T 5, T 5.6-7, BO 3.7, fig 3.28
20. F  4/6 Stack frame, recursive assembly functions, fact7.s BO 3.7, T 5.6-7, x86 summary #2
21. M 4/9Stack frame cont'd, factn.s, tri-state-buffers BO 3.7, T 5.6-7, T 3.3.4
22. W 4/11Bomb lab, debugging with gdb GDB doc; guides by Pete and Beej
23. F  4/13Tips for HW 7, examples, memory organization T 3.3.4-6
24. M 4/16Caches, cache organization *T 4.5.1, BO 6.2-3, figs 6.16, 21, 23, 38
25. W 4/18Cache organization, memory mountain BO 6.4, 6.6
26. M 4/23Cache summary, HW 8, buffer-overflow attacks, RAM circuit BO 6.4, 3.10.3-4
27. W 4/25 Writing cache-friendly code, optimizing performance BO 6.5, 5.1-6, CMU lect 10: 1-27
28. F  4/27Microarchitecture, pipelines, loop unrolling/splitting, branch prediction BO 5.7-11, T 4.5.2-4.8, CMU lect 10: 28-56
29. M 4/30Floating point representations, Σniac circuit *T 4.5.2, T App B, Martin 2.2.4, HW 9
30. W 5/2Σniac circuit, HW 8 review, preventing buffer overflow attacks HW 9, BO 3.10.4
31. F  5/4Virtual memory, Meltdown and Spectre BO 9, T 6.1, CMU lect 17
32. M 5/7Σniac control signals; chip design, NIM HW 10, slides, Wikipedia:NIM, *video 1, *video 2
33. W 5/9Computer hardware, Q&A Q&A worksheet
34. F  5/11ARM architecture and assembly, examples T 5, ARM links
35. M 5/14Course summary, final exam review Study guide, practice question

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