Intel Core i7 Die

CS 202 - Fall 2012

Computer Architecture

Announcements

Final Exam: Self-scheduled (pick up at my office), Monday 12/10, 1pm - Saturday 12/15, 5pm.
The exam is 3 hours (plus an extra 60 minutes if you need them), open book / notes. You may not use a computer or access material online during the exam.

Homework

  1. Homework 1, due Monday 9/17. Solutions.
  2. Homework 2, due Monday 9/24. Solutions.
  3. Homework 3, due Monday 10/1. Solutions. Runlong Contest Results.
  4. Homework 4, due Monday 10/8. Solutions.
  5. Homework 5, due Friday 10/19. Solutions.
  6. Homework 6, due Monday 10/29. Solutions.
  7. Homework 7, due Monday 11/5. Solutions.
  8. Homework 8, due Monday 11/12. Solutions.
  9. Homework 9, due Monday 11/19. Solutions and timing results.
  10. Homework 10, due Wednesday 11/28 and Friday 11/30. Solutions.
  11. Homework 11, due Friday 12/7 at midnight.

Lectures

DayTopicsReading
1.   M 9/10      Course info, overview, levels of computer languages      T 1, BO 1
2.   W 9/12Number systems, binary, hex, converting between bases         T A, Martin 2.1, Wikipedia:Gibibyte
3.   F  9/14Fixed precision numbers, overflow, C, sizetest.c, testprog.c     T A, Martin 2.2-4, [BO 2.1-3]
4.   M 9/17Boolean operations, C, baseB2dec.c Martin 2.5, T 2-2.3.6, BO 1
5.   W 9/19C: arrays, strings, pointers, computer organization T 2, BO 1
6.   F  9/21Fetch-decode-execute, instruction encoding, ΣniacBO 1, T 2, T 5.3 Σniac handout
7.   M 9/24Σniac programming, abs.z Σniac handout
8.   W 9/26 HW 3, zniac.c, intro to Pentium, asmprog.s, main.c BO 3-3.5, T 2.1.3, 5.3-4
9.   F  9/28Stack frame, push, pop, parameters, mult.s      BO 3-3.7, T 5.3-4
10. M 10/1Shift, leal, comparing, branching, sum1to5.s, sum1to5b.s BO 3.4.1, 3.5.1, 3.6
11. W 10/3Branching cont'd, jump encodings, debugging with ddd BO 3.6, 3.8, ddd manual
12. F  10/5Arrays, arrmax.s BO 3.8
13. M 10/8Digital circuits, LogicWorks T 3.1, BO 4.2.1-2
14. W 10/10 Multiplexers, decoders, adder/subtractor T 3.2, HW 5
15. F  10/12 Online lecture: Quiz 4, Circuit aesthetics, LW subcircuits LW 6
16. W 10/17Sequential circuits: latches, flipflops, asynchronous counter T 3.3
17. F  10/19JK flipflop, synchronous counter, register T 3.3
18. M 10/22Exam Q&A, multiplier HW 6, T 3.3
19. W 10/24Movie: Silicon Run Lite
20. F  10/26Shift register, stack frame, function calls, hello.s, hello2.s BO 3.7, T 5.6-7
21. M 10/29Recursive assembly functions, fact7.s, factn.s, factn2.s BO 3.7, T 5.6-7
22. W 10/31Memory, ROM, tri-state-buffers T 3.3.3-6
23. F  11/2Caches, cache organization BO 6.2-4, T 4.5.1
24. M 11/5Cache org, writing cache-friendly code, memory mountain BO 6.4-6
25. W 11/7Buffer-overflow attacks, alignment HW 8, BO 3.12, 3.9.3
26. F  11/9 Optimizing performance, microarchitecture, pipelines BO 5-5.7
27. M 11/12Branch prediction, loop unrolling and splitting, RAM T 4.5.2-4.8, BO 5.8-11
28. W 11/14Makefiles, .h files, inline assembly, measuring CPEs, malloc     inline.c, BO ASM:EASM, HW 9 code
29. F  11/16Floating point representations T App B, Martin 2.2.4
30. M 11/19Σniac circuit HW 10
31. M 11/26Floating point operations BO ASM:X87
32. W 11/28Σniac control signals HW 11
33. F  11/30Chip design, NIM Wikipedia:NIM
34. M 12/3MMX + SSE BO OPT:SIMD, ASM:SSE
35. W 12/5 x86-64, sum8.c, sum8long.c, virtual memory BO 3.13, 9; T 6.1
36. F  12/7Course summary, final exam review

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