CS 202 - Homework 11 - 11/30/07

Due: Friday, 12/7/07, at midnight.

This homework completes the Sniac circuit project. You should continue working in the same groups as for HW 10 (or by yourself). I only need one submission per group. On your submission, please write down how much time it took you. Submit your homework by midnight on Friday, December 7. If you have a 24h extension left, you have until Saturday. Note: besides the paper submission, you'll have to submit your circuit electronically using the course dropbox on the CLASSES server (more details below).

Sniac II circuit - control signals

1. Implement a synchronous 2-bit counter from 2 J-K flipflops, followed by a 2-to-4 decoder to generate the timing signals t0, t1, t2, t3.

2. You'll also need 2 J-K flipflops for the signals "E" and "run". The inputs of the "E" FF are "set E" and "reset E"; the outputs are "E" (not-inverted) and "I" (inverted). The "run" should be set (asynchronously) upon a "reset" signal, and reset upon a "halt" signal. (All other flipflops should be reset asynchronously upon a "reset" signal.) Use inverted output of the "run" FF in an OR gate together with the (input) clock signal to generate the global clock signal "c". This way, the circuit will start running upon a reset, and stop when a halt signal is reached.

3. Using the timing diagram at the end of this handout, derive equations for all control signals. The "inputs" in your equations should be the timing signals t0, t1, t2, t3, I, and E, the three opcode bits OP2, OP1, OP0, and A7 (the highest bit of the accumulator). The outputs should be all signals that appear in the table. For example, the ld_OP signal can be written as I & t1. Similarly, the sub signal can be written as !OP2 & !OP1 & OP0 & E & t2. Sometimes it will be easier to introduce "temporary variables", e.g., a signal store = !OP2 & OP1 & OP0.

   Once you have all your equations, implement them using simple AND, OR, and NOT gates and add them to the circuit. Be careful: in the circuit, the signal names are slightly different.

4. The Sniac III - build the next generation Sniac!!
   Implement a new instruction for the unused opcode 6 (110). At the very least, implement a "clear A" instruction. EXTRA CREDIT will be awarded for more complicated instructions. For example, you could implement a "load immediate" instruction that loads a 5-bit number sign-extended into A. Or maybe an "add immediate" instruction would be more useful. Perhaps best: an "add immediate" instruction that is interpreted as "clear A" if the addend is 0.

   Other extra-credit opportunities (harder...):

   • Speed up the circuit by using minimum-length cycle sequences.
   • See if you can get rid of the B register (also could yield speed-up).
   • Create an 8-bit multiplier and add a "mult" instruction.
   • Make the Sniac a 10-bit or 12-bit machine with 4-bit opcodes.
   • Whatever else you can come up with...
   If you do any of the above, please hand in a written description of what you did in addition to a printout of the circuit.

What to hand in

1. A printout of your top-level Sniac circuit, including the circuitry for the control signals. Include printouts of any subcircuits that are new or modified since your hw 10 submission.

2. A 1-page description of your control circuit, including equations for all control signals, and an explanation and timing diagram of your new instruction.

3. An electronic submission of your Sniac circuit. Rename your top-level .cct file with your own name, and drop it into the course dropbox

   \\CLASSES\VOL1\Fall07\CSCI0202A\DROPBOX

   If you cannot access the dropbox for some reason, you can send me the file as an attachement by email. But try the dropbox first!