CS 202 - Fall 2007

Computer Architecture

Announcements

Final Exam: Self-scheduled (pick up at my office!), Tuesday 12/11 - Tuesday 12/18.
The exam is 3 hours, open book / notes. You may not use a computer or access material online during the exam.

LogicWorks printing tips

Homework

  1. Homework 1, due Monday 9/17. Solutions.
  2. Homework 2, due Monday 9/24. Solutions.
  3. Homework 3, due Monday 10/1. Solutions. Runlong Contest Results.
  4. Homework 4, due Monday 10/8. Solutions.
  5. Homework 5, due Wednesday 10/17. Solutions.
  6. Homework 6, due Monday 10/29. Solutions.
  7. Homework 7, due Monday 11/5. Solutions.
  8. Homework 8, due Monday 11/12. Solutions.
  9. Homework 9, due Monday 11/19. Solutions and timing results.
  10. Homework 10, due Friday 11/30. Solutions.
  11. Homework 11, due Friday 12/7 at midnight.

Lectures

DayTopicsReading
1.   M 9/10       Course info, overview, levels of computer languages      T 1, BO 1
2.   W 9/12Number systems, binary, hex, converting between bases         T A, Martin 2.1, Wikipedia:Gibibyte
3.   F  9/14Fixed precision numbers, overflow, C, sizetest.c, testprog.c T A, Martin 2.2-4, [BO 2.1-3]
4.   M 9/17Movie: Silicon Run Lite T 2-2.3.6
5.   W 9/19Boolean operations, C, baseB2dec.c Martin 2.5, T 2, BO 1
6.   F  9/21C: arrays, strings, pointers, computer organization BO 1
7.   M 9/24Fetch-decode-execute, instruction encoding, SniacT 5.3, Sniac handout
8.   W 9/26Sniac programming, HW 3, abs.z, zniac.c Sniac handout
9.   F  9/28 Intro to Pentium, asmprog.s, main.c BO 3-3.5
10. M 10/1Assembly functions with parameters, stack, push, pop, mult.s      BO 3-3.7, T 5.3-4
11. W 10/3 Callee/caller-saved regs, shift, leal, comparing, branching, sum1to5.s     BO 3.4.1, 3.5.1, 3.6
12. F  10/5Branching cont'd, sum1to5b.s, debugging with ddd, arrays, arrmax.s BO 3.6, 3.8
13. M 10/8Digital circuits, LogicWorks T 3.1, BO 4.2.1-2
14. W 10/10 Multiplexers, decoders, adders T 3.2
15. F  10/12 Adder/subtractor, LogicWorks subcircuits, flipflops HW 5, LW 6, T 3.2.4-3.3.3
16. M 10/15Sequential circuits: latches, flipflops T 3.3.3
17. W 10/17JK flipflop, counters, T 3.3.3
18. F  10/19Multiplier, registers, shift registers HW 6, T 3.3.3
19. W 10/24Exam Q&A, Chip design, NIM Wikipedia:NIM
20. F  10/26Stack frame, function calls, hello.s, hello2.s BO 3.7, T 5.6-7
21. M 10/29Recursive assembly functions, fact7.s, factn.s, factn2.s BO 3.7, T 5.6-7
22. W 10/31Saving locals on stack, memory, ROM and RAM T 3.3.3-6
23. F  11/2Tri-state buffers, memory, caches BO 6.2-4, T 3.3.4-6, 4.5.1
24. M 11/5Cache organization BO 6.4, T 4.5.1
25. W 11/7Writing cache-friendly code, alignment, buffer-overflow attacks           BO 6.6, 3.10, 3.13
26. F  11/9Optimizing program performance BO 5-5.6
27. M 11/12Microarchitecture, pipelines BO 5.7, 5.12, T 2.1.5, 4.5.2-4.6.1
28. W 11/14Branch prediction, loop unrolling and splitting T 4.5.2-4.8, BO 5.8-11
29. F  11/16Makefiles, .h files, inline assembly, measuring CPEs inline.c, BO 3.15, HW 9 code
30. M 11/19Floating point representations T App B, Martin 2.2.4
31. M 11/26Sniac circuit HW 10
32. W 11/28Floating point operations BO 3.14
33. F  11/30 Sniac control signals HW 11
34. M 12/3MMX / SSE instructions, fadd.c, faddi.c, addF4, addF, hw9
35. W 12/5Memory management, virtual memory, x86-64 BO 10, T 6.1
36. F  12/7Course summary, final exam review

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