pete > courses > CS 202 Spring 24 > Lecture 07: storage elements

Lecture 07: storage elements

Goals

we’ve covered physics, transistors, logic gates, and some combinational logic

now we get to storage elements!

storage elements are… weird, at least in structure

first up: R-S latch (or S-R latch)

rs_latch.circ

pair of NAND gates with feedback

starts in "quiescent" state, with both R and S set to 1

toggle S, Q changes to 1 (not-Q changes to 0)

toggle R, Q changes to 0 (not-Q changes to 1)

note that if it’s set to 0, toggling R later does nothing

therefore, toggling S causes this circuit to store the value 1

and toggling R causes it to store the value 0

S for set

R for reset

Q is the stored bit

not-Q is for convenience (and it’s otherwise free)

example of an "active-low" circuit, meaning it does its thing when it sees a 0

(opposite: "active-high", does its thing when it sees a 1)

first: note that this circuit is NOT combinational!

at one point, its inputs were 1 and 1, and its output was 0 and 1

then later, its inputs were 1 and 1 again but its output was 1 and 0

to be combinational, the output must be entirely determined by the inputs at a single moment in time; it cannot depend on the past

this circuit depends on the pasta

but how on earth does it work?

Logisim lets us watch the electrical signal propagate through the circuit

not totally accurate, though

Logisim presents us with an abstraction of time, which it calls steps

during one step, current will flow through a single wire or a single logic component (eg, a gate)

when you start up Logisim, simulated electricity is always flowing, which is why changing the value of an input pin has an immediate effect

to see how this circuit works, we have to stop that automatic flow of electricity: in the Simulate menu, UNselect "Auto-Propagate"

now, to let electricity flow ahead one step, we click "Single-Step Propagation" in the Simulate menu (or use the associated keyboard shortcut)

if we click it now, nothing seems to happen because there are no changes in the inputs

but if we click the S input, we see that the input pin itself is now producing a zero, but that the wire connected to the input is still bright green, indicating that it carries a 1

if we click Single-Step Propagation, we see that the wire now changes to dark green, indicating it carries a zero, and also both ends of the wire are marked by blue circles

these blue circles mean "the value of this wire has changed"

if we keep clicking Single-Step Propagation, we see that the circuit eventually reaches the stable state where Q is 1 and not_Q is 0

the circuit works precisely because the electricity takes time to propagate

if electricity flowed instantaneously, this circuit would never settle

note that R and S must never be 0 at the same time

if that happens, both Q and not-Q are 1, which violates the "rules" of behavior for this circuit

how can we make sure this doesn’t happen?

can we construct some circuitry that will prevent R and S from both being 0 at the same time?

one way: use an inverter to make sure R is always not-S

BUT this isn’t strictly correct

because the electricity takes longer to go through the inverter than through the bare wire

so there will be an instant where the outputs may be the same

but that’s okay (in this circumstance) because they will stabilize very shortly thereafter

but we’ve lost the ability to set or reset the stored bit

the stored bit now directly follows the value of S, which kinda defeats the purpose

gated D-latch

gated_d_latch.circ

stores a value whenever WE (write-enable) is 1

guarantees S and R are never both 0

and stores a value when we want it, not all the time

(draw graph of WE over time)

this circuit is "level-triggered"

meaning it does something (ie, "is triggered") based on the level (ie, whether it’s high or low) of the WE wire

we might want instead to store a value at an instant

(draw and-gate fed by WE and not-WE on board)

again takes advantage of fact that electricity propagates slower through inverter

use this to control the WE signal

and we have a D flip-flop

d_flip_flop.circ

(draw graph of WE over time, show when Q changes)

this circuit is therefore "edge-triggered"

it does its thing on the rising edge of the WE signal

(the opposite of rising edge is falling edge)

for this to work in Logisim, we have to add an extra step of delay

this particular circuit is so popular that Logisim provides a black box implementation of it: Memory -> D Flip-Flop

two types of storage elements

latches are level-triggered

flip-flops are edge-triggered

reminder: exceptions to EVERYTHING

lots of this nomenclature isn’t fully standardized, but these meanings will do for this class

(if you mess around with this stuff in the real world, make sure you check what they mean)

we’ve broken through the abstraction layers we’ve built up!

but we built circuits that remember

we now have memory!

Logisim has black boxes for all of these

next: bigger and better

Definitions

The following definitions introduced in this lecture are fair-game for future quizzes. You will be expected to give the exact definition as provided in these lecture notes.

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