pete > courses > CS 202 Spring 24 > Tier 2, Phase 2, Problem 03: ARM32 condition-code register
Tier 2, Phase 2, Problem 03: ARM32 condition-code register
For this problem, you will construct a component for an ARM32 processor whose precise use will not yet be apparent, but will be necessary to construct the full processor (which is the Phase 2 project). As such, implement its behavior according to the specification below and try to suppress questions about "why?"
Your submission will consist of two files, described in detail below:
- condition_codes.circ
- test-vector.txt
Note that a working solution to this assignment will be necessary to complete the Phase 2 project.
Interface & Behavior
The file condition_codes.circ must contain a subcircuit named main with the following inputs and outputs:
| name | width | direction |
|---|---|---|
| operand | 32 bits | in |
| ld_cc | 1 bit | in |
| N | 1 bit | out |
| Z | 1 bit | out |
| P | 1 bit | out |
And the following behavior:
When the circuit is reset, all outputs should be 0.
On the rising edge of "ld_cc": if "operand" is negative, the "N" output should become 1; if "operand" is not negative, the "N" should become 0.
On the rising edge of "ld_cc": if "operand" is zero, the "Z" output should become 1; if "operand" is not zero, the "Z" should become 0.
On the rising edge of "ld_cc": if "operand" is positive, the "P" output should become 1; if "operand" is not positive, the "P" should become 0.
The outputs should only ever change on the rising edge of "ld_cc". That is, when "ld_cc" goes high, this component should remember whether its input at that instant is negative, zero, or positive. Even if "operand" changes in the future, the "N", "Z", and "P" bits should stay as they are unless/until "ld_cc" again goes high.
(Note: "ld_cc" is "load condition codes": that first character is a lowercase ell, not a one or a capital eye.)
Note that we will not be able to test (and therefore give feedback on) the functionality of your circuit unless its inputs and outputs are exactly as specified above.
Restrictions
You are limited to components from the following Logisim libraries:
- Wiring
- Gates
- Plexers
- Memory
You may add as many subcircuits as you deem appropriate.
Testing
Since this circuit is sequential logic, Logisim’s built-in testing functionality will not be helpful. You must still submit a test-vector.txt file that adequately tests your circuit. When devising your tests, here are some things to keep in mind:
You may assume all built-in components provided by Logisim function correctly.
As a result, your tests should focus on how you’ve connected together those components. Given the design of your circuit and the components it comprises, how might you have misconnected things? Where might a wire have gone astray? Write tests that verify that your wires go where you want them to go and do what you want them to do.
Submission Instructions
Copy the condition_codes.circ and test-vector.txt files to weathertop and then run:
$ 202 submit t2p2p03 condition_codes.circ $ 202 submit t2p2p03 test-vector.txt
Submissions will not be accepted after 2pm on Wednesday, 10 April.