pete > courses > CS 202 Spring 24 > Tier 2, Phase 2, Problem 01: ARM32 register file
Tier 2, Phase 2, Problem 01: ARM32 register file
For this problem, you will construct a register file for an ARM32 processor. It will contain 16 32-bit registers and support the behaviors we have discussed in class: reading from two arbitrary registers, writing to an arbitrary register, and updating the program counter (r15).
Your submission will consist of two files, described in detail below:
- register_file.circ
- test-vector.txt
Note that a working solution to this assignment will be necessary to complete the Phase 2 project.
Interface & Behavior
The file register_file.circ must contain a subcircuit named main with the following inputs and outputs:
| name | width | direction |
|---|---|---|
| Rd | 4 bits | in |
| Rn | 4 bits | in |
| Rm | 4 bits | in |
| Rd_val | 32 bits | in |
| Rn_val | 32 bits | out |
| Rm_val | 32 bits | out |
| new_pc | 32 bits | in |
| we | 1 bit | in |
| clk | 1 bit | in |
| r0 | 32 bits | out |
| r1 | 32 bits | out |
| r2 | 32 bits | out |
| r3 | 32 bits | out |
| r4 | 32 bits | out |
| r5 | 32 bits | out |
| r6 | 32 bits | out |
| r7 | 32 bits | out |
| r8 | 32 bits | out |
| r9 | 32 bits | out |
| r10 | 32 bits | out |
| r11 | 32 bits | out |
| r12 | 32 bits | out |
| r13 | 32 bits | out |
| r14 | 32 bits | out |
| r15 | 32 bits | out |
And the following behavior:
At all times, "Rn_val" and "Rm_val" should reflect the values stored in registers specified by "Rn" and "Rm", respectively.
Likewise, at all times, "r0" through "r15" should reflect the values stored in registers "r0" through "r15" (these are for debugging/introspection).
On rising edge of "clk", if "we" is 1, register specified by "Rd" should store value on "Rd_val" input.
On rising edge of "clk", register 15 should store the value on "new_pc" input.
You may assume that "Rd" will never be set to 1111.
Note that we will not be able to test (and therefore give feedback on) the functionality of your circuit unless its inputs and outputs are exactly as specified above.
Note also that the collection of outputs above is indeed excessive: they will, however, come in handy when debugging the behavior of the full processor (which is the Phase 2 project).
Restrictions
You are limited to components from the following Logisim libraries:
- Wiring
- Gates
- Plexers
- Arithmetic
- Memory
You may add as many subcircuits as you deem appropriate.
Testing
Since this circuit is sequential logic, Logisim’s built-in testing functionality will not be helpful. You must still submit a test-vector.txt file that adequately tests your circuit. When devising your tests, here are some things to keep in mind:
You may assume all built-in components provided by Logisim function correctly.
As a result, your tests should focus on how you’ve connected together those components. Given the design of your circuit and the components it comprises, how might you have misconnected things? Where might a wire have gone astray? Write tests that verify that your wires go where you want them to go and do what you want them to do.
Submission Instructions
Copy the register_file.circ and test-vector.txt files to weathertop and then run:
$ 202 submit t2p2p01 register_file.circ $ 202 submit t2p2p01 test-vector.txt
Submissions will not be accepted after 2pm on Wednesday, 10 April.