pete > courses > CS 202 Spring 24 > Tier 2, Phase 1, Problem 08: 8-bit counter

Tier 2, Phase 1, Problem 08: 8-bit counter

In the traffic light system, we used a counter, a circuit that output a number encoded as unsigned binary, which incremented by 1 whenever its clock input went high. For this problem, you will implement a counter that will do just that.

Testing for this assignment is less straightforward, as Logisim-Evolution does not support testing sequential logic. Nor does it make sense to test this circuit using the "enumerate a bunch of input combinations and their corresponding outputs" approach. You will still create and submit a test-vector.txt file, but neither you nor the graders will run it using the built-in testing functionality. Instead, we will have to use our imagination.

Your test vector file should contain columns for every input and output except the clock input. Each line of the file should reflect one state of the circuit, with the assumption that the clock will be toggled after checking each line. You may also (read: should) insert comments that indicate when to reset the circuit.

Here is an example that does not correspond to the behavior of the circuit you will create, but is hopefully illustrative of what I mean:

A B C out
# reset
0 0 0 0
0 1 1 0
0 1 0 1
1 0 0 1

To "run" that test vector, we would do so manually. We would first reset the circuit and verify that "out" is 0. Then we would set both B and C to 1, toggle the clock, and verify that "out" is 0. Then we would set C back to 0, toggle the clock, and verify that "out" is 1. Finally, we would set B to 0, A to 1, toggle the clock, and verify that "out" is 1.

Submission Requirements

You will submit a single Logisim-Evolution circuit file and a single text file containing tests that verify your circuit’s correctness. The name of the circuit file must be counter8.circ and the name of the test file must be test-vector.txt.

The main circuit within counter8.circ must have one 8-bit input labeled "max", one 1-bit input labeled "clk", and one 8-bit output labeled "value". When the circuit is reset (Simulate -> Reset Simulation), the "value" output should be 0. On every rising edge of the "clk" input, the "value" output should increase by 1 (interpreted as an unsigned binary integer). If increasing the "value" input would cause it to equal or exceed the "max" input, the "value" input should instead become 0.

You are limited to components from the following Logisim libraries:

You may add as many subcircuits as you deem appropriate.

Submission Instructions

Copy the counter8.circ and test-vector.txt files to weathertop and then run:

$ 202 submit t2p1p08 counter8.circ
$ 202 submit t2p1p08 test-vector.txt

Submissions will not be accepted after 2pm on Friday, 15 March.

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